PCI Express: Interconnect of the future

PCI Express, previously known as 3rd Generation I/O (3GIO), is all set to replace PCI and take general IO connectivity into the next decade.

PCI Express seeks to fulfil a number of requirements.

It is designed to support multiple market segments and emerging applications, as a unifying I/O architecture for Desktop, Mobile, Server, Communications, Workstations and Embedded Devices. It is not just for the desktop, like the original PCI specification was designed to be.

With regards to cost in both high and low volumes, the target is to come in at or below PCI cost structure at the system level. A serial bus requires fewer traces on PCBs, easing board design and increasing efficiency by allowing more space for other components.

It has a PCI Compatible software model, where existing Operating Systems should be able to boot without any changes. In addition, configuration and device drivers for PCI Express are to be compatible with existing PCI.

Performance scalability is achieved through increasing frequency and adding "lanes" to the bus. It is designed for high bandwidth per pin with low overheads and low latency. Multiple virtual channels per physical link are supported.

As a point-to-point connection, it allows each device to have a dedicated connection without bus sharing.

Other advanced features include
- ability to comprehend different data structures,
- low power consumption and power management features
- quality of service policies
- hot swappability and hot pluggability for devices
- data integrity and error handling end-to-end and at the link level
- isochronous data transfer support
- host-based transfers through host bridge chips and peer-to-peer transfers through switches
- packetized and layered protocol architecture