Intel Test Results: OCZ 3700EB
To be considered stable for test purposes, Quake3 benchmark, UT2003 Demo, Super PI, Aquamark 3, and Comanche 4 had to complete without incident. Any of these, and in particular Super PI, will crash a less-than stable memory configuration.OCZ 3700EB (DDR466) - 2 x 512Mb Double-Bank | |||||
Speed | Memory Timings & Voltage | Quake3 fps | Sandra UNBuffered | Sandra Standard Buffered | Super PI 2M places (time in sec) |
400DDR 800FSB |
2.5-2-3-5 2.5V |
322.0 | INT 2752 FLT 2769 |
INT 4460 FLT 4452 |
131 |
433DDR 866FSB |
2.5-2-3-5 2.5V |
350.2 | INT 3024 FLT 3007 |
INT 4838 FLT 4837 |
121 |
466DDR 933FSB |
3-2-3-5 2.5V |
377.9 | INT 3214 FLT 3218 |
INT 5201 FLT 5202 |
113 |
500DDR 1000FSB |
3-2-3-5 2.75V |
403.5 | INT 3484 FLT 3486 |
INT 5581 FLT 5585 |
105 |
524DDR 1048FSB |
3-2-3-6 2.85V |
415.0 | INT 3639 FLT 3703 |
INT 5922 FLT 5891 |
100 |
At DDR466, OCZ 3700EB was able to run our complete memory test suite at SPD timings. The DIMMs were stable at the standard 2.5V to 2.6V at the rated timings at DDR466, which is even lower voltage than specified. As we saw in our earlier EB review, the memory can handle voltage and rewards higher voltage with even better timings at the high end. We achieved the best performance on the Intel test bed with the lowest Cycle Time (tRAS) that we could run. Therefore, tRas on Intel chipsets should be set at 5 or 6 for the best performance, rather than the 8 set in SPD.
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RyanVM - Wednesday, May 19, 2004 - link
What kind of performance impact does dropping the Hypertransport multiplier really have? It would be nice to see a comparision of say HT 1000Mhz @ 5x200Mhz and 4x250Mhz to see just what a difference it really makes.KillaKilla - Wednesday, May 19, 2004 - link
Why are you guys still using the 9800 Pro, as opposed to the X800 XT? Wouldn't you want the entire bottleneck to be as much on the RAM as possible?